Makefile Structure

The primary purpose of the make program is to assist compilation and recompilation of a multi-file program, such that only those portions of the program are recompiled that require it. For example, if a header file is changed, then each source file which #includes that file must be recompiled. make provides an easy mechanism by which such dependencies (also called prerequisites) may be tracked.

Makefiles consist of rules which describe how to carry out commands. For example, a rule might explain how to compile a single source file, or how to link all the object files into the executable, or perhaps how to clean up all the object files. A rule has the following form

target: dependencies
        command
        command
        ...

The target is the name of the rule, e.g. the name of the program or file to be compiled. The first rule given in the Makefile is the default. The dependencies are the names of files (often names of other targets, as well) on which the construction of the target depends. A particular target does not necessarily have to have dependencies. The commands are the actual commands to be executed once all the dependencies are complete. Note that a <TAB> must be used to indent commands under the target name; if you use spaces or don't indent you'll get a (not entirely clear) error message. Makefiles may also contain variable definitions to make the file perhaps simpler.